As PCB routing density and signal frequency continue to rise, issues like signal integrity (SI) and electromagnetic compatibility (EMC) have become increasingly prominent, imposing stricter requirements on hardware design. In high-speed, high-frequency multilayer PCB design, the impact of via parasitic parameters on signal integrity cannot be ignored—making the application of back drilling technology an inevitable choice.
Back drill 1
Back drilling is a specialized via processing technique. In PCB manufacturing, standard plated through-holes (PTH) are first drilled and electroplated. Then, a second drilling operation is performed, using depth-controlled drilling equipment to remove the unused plated copper section of the via (known as the “stub”). The tolerance of back drilling is mainly affected by the precision of the back drilling equipment and the dielectric thickness tolerance.
As illustrated in the diagram, a signal trace is routed on Layer 11, with vias connecting both ends to the component side and solder side of the PCB for component mounting. In this setup, signals travel from Component A through the Layer 11 trace to Component B.
For the signal transmission path described above, the via acts as an extension of the signal trace. Without back drilling, the signal path includes the entire via—from the component side to the solder side.
In this unoptimized path, the via section from the solder side to Layer 11 serves no connection or transmission purpose. This redundant stub causes signal reflection, scattering, and delay, leading to signal distortion. A simple analogy is water flowing through a syringe: steady water flow can be achieved under uniform pressure, but an extra sealed inclined tube attached to the syringe disrupts the flow consistency—much like how a via stub distorts signal transmission.
In summary, the core function of back drilling is to remove redundant via stubs, eliminating signal reflection, scattering, and delay to prevent signal distortion. It is worth noting that every 1 mil increase in residual stub depth leads to approximately 0.25% higher signal loss.
Back drilling depth & target layers
The required depth for each back-drilled via must be clearly specified in manufacturing documents, along with the exact layer range (e.g., back drilling from Layer 14 to Layer 9).
Back drilling hole size
Typically, the diameter of the back-drilled hole is about 10 mils larger than the original PTH via.
Back drilling safety margins
The distance between the back-drilled hole and inner-layer traces must be at least 20 mils (10 mils is the minimum limit per IPC standards).
The minimum gap between adjacent back-drilled holes is 10 mils.
The clearance between the back-drilled hole and outer-layer pads should be at least 15 mils (20 mils per IPC-6012A requirements).
For through-hole components with back drilling, the annular ring of the back-drilled hole should be 4 mils larger than the original drill bit. Minor annular ring damage is generally acceptable, while the annular ring on the non-back-drilled side should remain intact.
The dielectric thickness between the drilled layer and the non-drilled layer must be 6–8 mils.
Residual stub depth should be minimized for optimal signal performance. Due to manufacturing tolerances (depth and board thickness variations), a residual stub of 4–8 mils is generally acceptable in mass production.
Due to inherent tolerances in drilling depth and board thickness, it is impossible to achieve 100% accuracy in meeting the exact depth requirements. When adjusting back drilling depth, the golden rule is “better shallow than deep”—sufficient safety margins must be maintained to avoid accidental open circuits on signal traces.
Assume the customer requires back drilling from the solder side down to Layer M. Following the “better shallow than deep” principle, the theoretical maximum drilling depth should fall between Layer M+1 and Layer M+2. The test pattern must be designed to ensure the back-drilled hole is open to Layer M+2 and connected to Layer M+1.
The back drilling depth can be verified by testing the connectivity between test points A, B, C, and D:
If Test Point A is connected to both B and C: The drilling depth is too shallow.
If Test Point A is open to both B and C: The drilling depth is too deep. Further testing is required between A and D: If A and D are open, the signal trace has been damaged and the board must be scrapped; if A and D are connected, the board still meets requirements, but the drilling process must be adjusted to reduce depth.
If Test Point A is connected to C but open to B: The back drilling depth is optimal (between Layer M+1 and M+2), and mass production can proceed.
Driven by the digital transformation of industries, signal transmission speeds and frequencies are soaring, and high-power amplifiers are widely adopted—making signal integrity and EMC critical concerns. Traditional PCBs can no longer meet the demands of high-speed, high-frequency circuits. Leading tech companies have validated that redundant via stubs are a major source of signal degradation, and back drilling technology offers a cost-effective solution to optimize signal performance for high-speed, high-frequency applications.
Back drill 2
FUMAX specializes in high-speed, high-density PCB manufacturing with advanced back drilling capabilities. Our state-of-the-art equipment ensures tight tolerance control (residual stub depth as low as 4 mils) for critical applications like AI servers, 5G communication devices, and industrial automation systems. We provide end-to-end support from design optimization to mass production, ensuring your PCBs deliver exceptional signal integrity and reliability.
Contact our engineering team to discuss your back drilling requirements:
