In many projects, pick-and-place goes smoothly.
AOI looks fine.
The boards look perfect.
And then—during functional test, burn-in, or even field use—problems start to appear.
Reflow oven 1
Intermittent failures.
Unstable signals.
Boards that pass today and fail tomorrow.
Very often, the root cause is not component placement.
It’s reflow soldering.
Reflow is one of the most underestimated stages in PCB assembly. It doesn’t decide whether components are soldered—it decides whether those solder joints will survive real life.
This is one of the most frustrating issues for engineers.
From the outside, everything looks normal. The solder joints are shiny, well-shaped, and pass AOI. But electrically, something is wrong: contact resistance drifts, signals glitch, or failures appear only at certain temperatures.
What’s really happening?
Cold solder joints, partial wetting, or insufficient reflow time
Cold solder joints 1
A solder joint can look good while still having poor metallurgical bonding. AOI cannot detect grain structure problems or incomplete intermetallic formation. Only the reflow profile—especially time above liquidus—determines that.
Real-world case:
One customer had boards that passed FCT but failed randomly after thermal cycling. The fix wasn’t a design change—it was extending the soak and peak dwell time by less than 10 seconds.
Engineers often say:
“EVT was fine. DVT was fine. Why does this only happen in production?”
Head-in-Pillow (HiP) defects are a classic example.
This issue occurs when the solder ball and solder paste melt at different times and never properly merge. It’s not a placement issue—it’s a thermal synchronization problem.
Contributing factors include:
Painful reality:
HiP defects are invisible to AOI. X-ray is the only reliable detection method.
Many teams only discover this after shipment.
Another common mystery:
“Why does the power section look perfect, but the MCU area is problematic?”
The answer is thermal mass.
Large copper pours, ground planes, connectors, and shields absorb heat very differently from fine-pitch IC areas. During reflow, some areas reach proper temperature while others lag behind.
If the layout is unbalanced, you get inconsistent solder quality across the board—even with a “correct” reflow profile.
This is why manufacturers sometimes recommend:
These are not cosmetic suggestions—they are thermal ones.
Many people blame pick-and-place for tombstoning. In reality, most tombstoning happens during the early reflow stage.
The real cause:
If one side wets earlier, surface tension pulls the component upright.
Important takeaway:
This is a pad design + thermal behavior issue, not a nozzle accuracy issue.
At room temperature, a PCB may look flat.
At 235–245°C, it can behave very differently.
For low-stand-off packages like BGA and QFN, even slight warpage can:
This is why manufacturers care about:
It’s not overengineering—it’s damage prevention.
This is one of the hardest lessons in manufacturing.
Reflow soldering is extremely sensitive to system-level variation:
Reflow soldering process 1
In a lab environment, everything is controlled. On a production line, everything moves.
Reflow is not just a process—it’s a stability engineering problem.
Engineers often ask:
“Why can’t we just run it faster?”
Because speed increases:
A conservative reflow profile is not inefficiency—it’s risk management.
Reflow soldering is not a black box.
A good EMS partner explains thermal behavior instead of just “running standard settings”.
This matters most in:
Most reflow problems are not mysterious—they’re just rarely explained.
